Latest Insights
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Optimal Design of a High-Speed LVCMOS Output Driver
Published October 24, 2025 • Topics: I/O, Impedance Matching, PVT Control
An in-depth look at design of LVCMOS drivers, impedance matching and sizing of transistors in modern I/O buffers.
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Optimal PFD Delay for Dual PFD in Fractional N-PLLs
Coming Soon • Topics: PLLs, Phase Noise, Frequency Synthesis
Analyzing the trade-offs and crucial mathematical relationship between PFD delay and spur performance in advanced Fractional-N PLLs.
Article in progress.
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Architecture for a Mismatch-resistant Delay Cell
Coming Soon • Topics: DLLs, Delay Cells, Mismatch-resistant
This article presents a novel architecture for a mismatch-resistant delay cell with extreme trim accuracy.
Article in progress.