Precision Analog Design Solutions

I help hardware and semiconductor teams architect, simulate, and validate high-performance analog circuits — from low-noise amplifiers to high-speed PLLs.

Professional Summary

Senior Analog Design Engineer with 3+ years of experience in circuit design and verification. Specialized in PLLs, LDOs, and high-speed I/O systems, with multiple patents pending in JEDEC-compliant LPDDR architectures. Skilled in designing automated verification flows. Strong academic foundation from IIT Madras.

Professional Experience

  • Micron Technology Inc.
    Senior Analog Design Engineer (Nov 2024 – present)
    • Patent Pending – Co-invented novel control logic for LPDDR I/O expanders, JEDEC-compliant.
    • Patent Pending – Invented a configurable PVT accurate delay cell for precise timing symmetry.
    • Designed multiple internal Low Dropout Regulators for receiver front-end, high-frequency digital RTL and PMIC chips.
    • Architected a novel weighted summation voltage comparator with optimzed delay across a wide linear range
    • Developed integrated Python–Verilog testbench for automated regressions to check for JEDEC compliance & signal integrity validation.
  • Texas Instruments Inc.
    Analog Design Engineer (July 2022 – Oct 2024)
    • Designed 200MHz LVCMOS Output Buffer (65nm CMOS) and developed novel test methodology.
    • Designed 15GHz channel divider, with very low phase noise floor (130nm BiCMOS).
    • Designed 15GHz Fractional-N frequency divider for space grade PLL (130nm BiCMOS).
    • Reduced charge pump phase noise and spurs in fractional division mode by mathematical modeling of delta-sigma modulator + PFD feedback loop.
    • Led output path phase noise improvement for space grade PLL; proven in silicon.
    • Implemented unified UVM-based System Verilog testbench for functional and AMS verification.
    • Performed full chip latch-up simulations for MEMs oscillator SoC.
  • Analog Devices Inc.
    Analog Design Intern (May 2021 – Aug 2021)
    • Explored gm/Id transistor sizing for amplifier design trade-offs.

Education

  • Dual Degree, Electrical Engineering
    Indian Institute of Technology, Madras (2017–2022)
    CGPA: 8.37/10
    • Graduated from one of India’s top colleges for analog design, renowned for industry-leading research and education.
    • Completed advanced coursework and projects under top professors including Prof. Shanthi Pavan, Prof. Nagendra Krishnapura, Prof. S. Aniruddhan, and Prof. Janakiraman V.

Research Experience

Projects (Selected)

  • Data Conversion Circuits: 3rd order Delta Sigma Modulator, 4-bit flash ADC.
  • Broadband Communication Circuits: Clock/data recovery, discrete-time equalizers, eye-diagram evaluation.
  • RFIC Design: LNA, Mixer, VCO, Power Amplifier in 130nm IBM process.
  • Two-stage fully differential amplifier with common mode feedback.
  • 8-bit Pipelined Carry Save Multiplier (22nm CMOS), layout and timing characterization.
  • RISC-V compliant processor in Verilog; accelerator for multiplication 🔗.
  • Automated small signal analysis with Python for DC gain, poles, and zeros 🔗.

Technical Skills

  • Languages: Python, Verilog, VerilogA, VerilogAMS, System Verilog (UVM), SKILL, C++, C
  • Tools: Cadence Virtuoso, MATLAB